1. Field of the Invention
The invention relates in general to a method of fabricating an electrostatic discharge (ESD) protection device, and more particular to a method of fabricating a self-aligned silicide (salicide) ESD protection device.
2. Description of the Related Art
An input signal is applied into the gate of a metal-oxide semiconductor (MOS) in an integrated circuits (IC). However, if the voltage of the input signal is too high, the gate oxide layer breakdowns. It is known that the breakdown voltage of silicon oxide is about 8*10.sup.6 V/cm. For example, a gate oxide layer has a thickness of about 15 nm, it cannot sustain a voltage more than 12 V. With an applied voltage higher than 12 V, the gate oxide layer breakdowns. Thus, if an integrated circuit with such a gate oxide layer is operated under a voltage of about 5 V, breakdown is not supposed to occur. However, there might be some external input signal with a higher voltage which will endanger the circuit and cause breakdown during operation. This kind of voltage source is normally caused from triboelectricity, that is, the electrostatic charges caused by the friction between objects. When one walks through a room, or takes an IC from a plastic bag, a voltage from hundreds to thousands of volts can be induced. If the high voltage is unintentionally applied to the pins of the IC package, breakdown may occurs, and the device is damaged immediately. Under this condition, the gate oxide cannot be operated normally and a device failure occurs.
To prevent the gate of a MOS component from being damaged, all MOS ICs are provided with certain protection circuits, which are normally applied in devices in very-large semiconductor integrated circuits. The protection circuits are normally arranged between the input/output pads on a chip and a gate of a transistor which is connected thereto.